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           cmos 在 無線電電子學 分類中 的翻譯結果: 查詢用時:0.182秒
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        cmos     
        相關語句
          互補金屬氧化物半導體
            A modulator for RF transmitter of 5-GHz WLAN has been realized using 0.18 μm CMOS technology in this paper.
            該調制器以改進的Gilbert單元為核心,采用0.18μm-CMOS(互補金屬氧化物半導體)工藝實現,電路模擬結果符合設計要求。
        短句來源
            The mixer, regarding improved Gilbert unit as the core, is realized by 0.18μm CMOS process. When the power supply is 1 V, the circuit works at 5.8GHz and achieves 12dB gain, 10dB noise figure (NF) and -12dBm 1dB-compression-point.
            該混頻器以改進的Gilbert單元為核心,采用0.18μm CMOS(互補金屬氧化物半導體)工藝實現,主要性能指標如下:工作電壓1.8V,工作頻率5.8GHz,增益12dB,噪聲10dB,1dB壓縮點-12dBm。
        短句來源
            Spectre simulation with 0.6 μm n well CMOS technology shows that the circuit has excellent ability of power rejection and process insensitive.
            采用 0 .6 μm n阱互補金屬氧化物半導體 (CMOS)工藝的spectre仿真結果表明 ,此電路對因電源電壓、工藝參數變化而引起的過熱保護閾值點漂移有很強的抑制能力 .
        短句來源
            SMIC 0.25 μm 1P3M CMOS process is applied in the design.
            本設計采用了中芯國際0.25μm 1P3M的標準互補金屬氧化物半導體(CMOS)工藝。
        短句來源
            A development of infrared focal plane array (IRFPA) complementary metal oxide semiconductor (CMOS) readout integrated circuit (ROIC) is introduced. The circuit principle of ROIC, time sequence of multiplexer, circuit parameter, layout design and technology analysis are described.
            介紹了一種紅外焦平面陣列( IRFPA)互補金屬氧化物半導體 ( CMOS)讀出集成電路 ( ROIC)的研制方案 ,敘述了讀出電路的電路原理及工作時序、電路參數設計、版圖設計及工藝分析。
        短句來源
          互補型金屬氧化物半導體
            Proposed in this thesis, base on 0.6μm CMOS technology, a 10-bit high performance low power pipelined analog-to-digital converter is designed and implemented.
            本論文所述設計中,基于0.6微米互補型金屬氧化物半導體(CMOS)工藝,設計并實現一種10-bit高性能、低功耗的流水線模擬-數字轉換器(ADC)。
        短句來源
            In order to implement an analog-to-digital converter(ADC) with pipeline structure of 10-bit high performance and low power dissipation,a design method based on 0.6 μm complementary metal-oxide-semiconductor(CMOS)mixed signal technology was proposed.
            為了實現10位高性能和低功耗的流水線模擬數字轉換器ADC,提出了基于0.6微米互補型金屬氧化物半導體(CMOS)混合信號工藝的電路設計方法.
        短句來源
            Realization of a Laser Range Finding Device Based on Thin Film Fully-depleted SOI CMOS Integrated Technology
            用全耗盡絕緣硅互補型金屬氧化物半導體集成技術實現一種激光測距電路
        短句來源
            Since the switched current technology is employed, this system is fully compatible with a standard digital Complementary metal oxide semiconductor (CMOS) technology, and is easily to be integrated in mixed analog digital system and implemented in very large scale integrated circuit (VLSI).
            由于采用開關電流技術,該系統電路可以直接采用標準的數字互補型金屬氧化物半導體(CMOS)工藝來實現,便于模、數混合集成,易于超大規模集成電路(VLSI)的制作。
        短句來源
          “cmos”譯為未確定詞的雙語例句
            Research on CMOS readout circuit for IRFPA
            紅外焦平面陣列CMOS讀出電路研究
        短句來源
            Study on New Structural High Performance CMOS Readout Circuits for IRFPA
            紅外焦平面陣列新結構高性能CMOS讀出電路研究
        短句來源
            CMOS Rf Devices Modeling and Low Noise Amplifiers Design
            CMOS射頻器件建模及低噪聲放大器的設計研究
        短句來源
            Design of Low-Voltage, Low-Power CMOS Radio-Frequency Low-Noise Amplifiers
            低電壓低功耗CMOS射頻低噪聲放大器設計
        短句來源
            Design of a CMOS Monolithic Σ-Δ Fractional Frequency Synthesizer
            CMOS單片集成的Σ-Δ小數頻率合成器設計
        短句來源
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        查詢“cmos”譯詞為用戶自定義的雙語例句

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          cmos
        Therefore, it shows great potential in application for characterizing USJ in the sub-65 nm technology node CMOS devices.
              
        The chip was fabricated in 0.35 μm 1P3M standard CMOS process.
              
        The time-temperature exposures (conditions) were similar to those experienced by SOS structures used in CMOS/SOS LSI technology.
              
        Promising CMOS ICs Based on Si/CaF2/Si Epitaxial Layers
              
        A test CMOS IC with a CoSi2gate and a CaF2gate dielectric was produced.
              
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        Described here is a new style, cardiac pacing system—an implantable pacemaker with the programmability of parameters. It consists of a programmer and an implantable pacemaker with a digital memorial element. Whenever an adjustment is neccessary, the pacemaker can be manipulated to a new stable state with the programmer emitting a series of coded pulses toward it. The process of adjustment is quick and noninvasive.The pacemaker is made by combining a CMOS circuit with monolithic integralted circuits into...

        Described here is a new style, cardiac pacing system—an implantable pacemaker with the programmability of parameters. It consists of a programmer and an implantable pacemaker with a digital memorial element. Whenever an adjustment is neccessary, the pacemaker can be manipulated to a new stable state with the programmer emitting a series of coded pulses toward it. The process of adjustment is quick and noninvasive.The pacemaker is made by combining a CMOS circuit with monolithic integralted circuits into a hybrid circuit, which is characterized by low dissipation, light weight and small size.

        本文介紹一種新型起搏系統——參數可調的埋藏式起搏器——的設計方案及實施技術.它由一個體外操縱器及一只帶有數字記憶(由CMOS電路組成)元件的埋藏式起搏器所組成.無論在起搏器埋植前或后,當需要調節參數(包括接通或關斷電源)時,可使用體外操縱器向起搏器發射一組編碼的磁脈沖,這組脈沖被埋藏式起搏器感受,記憶,從而控制起搏參數到一新的指定的狀態,并將這種狀態一直保持下去直到進行再次調節. 由CMOS電路及混合型集成電路組成的起搏器具有功耗低、體積小、重量輕的特點.十個月的臨床應用表明:調節靈活,性能可靠,療效良好.

        In electron watches, power consumption required is generally very low. For this purpose, the present article analyses the power consumption in the CMOS quartz oscillators under the through current and loading conditions, and the method of seletion of paramatcrs of the oscillator and the measures to be adopted are also presented.

        電手表要求功耗甚微。為此,本文分析了CMOS晶體振蕩器由導通電流及負載引起的功耗,并提出如何選擇參數及應采取的措施。

        Until now, the history of computer development has always been divided according to the advent of new devices introducing striking changes to main frame. However, once the multiple valued logic system is realized and their theories are applied, we shall have a high efficient computer architecture that will be bring a higher level to the computer technology.The advent of DYL integrated circuit[1,2] provides a new hope for realizing the possibility as mentioned above in our country.In this paper, we propose that...

        Until now, the history of computer development has always been divided according to the advent of new devices introducing striking changes to main frame. However, once the multiple valued logic system is realized and their theories are applied, we shall have a high efficient computer architecture that will be bring a higher level to the computer technology.The advent of DYL integrated circuit[1,2] provides a new hope for realizing the possibility as mentioned above in our country.In this paper, we propose that a linear AND-OR gate of Multiple Elemental Logic (DYL) is an excellent AND-OR gate of multiple valued logic. If combined with other circuits, a new multiple valued logic circuit will be constructed (MV-DYL for short). By the comparison and experiment it is proved that the MV-DYL circuits can obtain higher information density than binary DYL circuits under like condition of power-delay product, and it has more advantages of simpler structure, easier realization and higher reliability than ternary CMOS and MV-I2L circuits.

        以往科學家們總是以新器件的出現,及隨之使整機產生了驚人的變化來劃分計算機發展歷史。然而一旦多值邏輯系統付諸實現,多值邏輯學說得到應用,這種高效率的計算機結構的出現,將可能使計算機技術進入更高的水平。我國DYL集成電路的發明為實現上述目標提供了新的希望。 本文指出,多元邏輯中的線性“與或”門本質上就是一種很好的多值邏輯“與或”門。它與其他電路配合可以構成一種新的多值邏輯電路(簡稱為MV-DYL)。通過比較和實驗證明,MV-DYL電路在與二值DYL電路相同的功耗-時延積條件下,可以獲得更高的信息密度。MV-DYL電路比三值CMOS和多值I~2L電路結構簡單、容易制作和可靠性高。

         
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